1. Field of the Invention
The present invention relates generally to closed-loop timing circuits and more particularly to a frequency synthesizer for providing a clock in a channel chip for an embedded servo hard disk drive and in similar circuits.
2. Description of Prior Art
Timing circuits are used to generate high frequency periodic signals for a variety of different applications. For example, timing circuits are used in computers to generate a clock (a substantially constant pulse repetition frequency signal) for a microprocessor, a bus, and for various integrated circuits in a video adapter, a disk drive, etc.
Each of certain closed-loop timing circuits responds to a periodic input signal to produce a periodic output signal under control of an error signal determined by comparing the periodic input and output signals. Such closed-loop timing circuits are commonly found in read/write circuitry for a hard disk drive. A contemporary embedded servo hard disk drive typically includes a channel chip which includes multiple closed-loop timing circuits. One such closed-loop timing circuit (referred to herein as a timing recovery circuit) responds to a read signal to produce a read clock for recovering data. U.S. Pat. No. 5,278,702 discloses a timing recovery circuit within a data synchronizer for recovering data. Another such closed-loop timing circuit (referred to herein as a frequency synthesizer) produces a clock used by different circuits in different types of operations. In one type, namely write operations, this clock is used by write circuitry to set the channel rate. In another type, the timing recovery circuit uses this clock as a substitute for the read signal (for example, during a seek in an embedded servo disk drive).
A contemporary hard disk drive utilizes zone banding for data to provide high capacity, and substantial research and development work has been, and continues to be, devoted to developing enabling technology for a zone-banded servo. As for zone banding generally, whether for data or for servo, its advantage resides in providing higher linear bit density recording. In older disk drives that did not employ any zone banding, the data was recorded at substantially the same channel rate for every track on the recording surface. Because the circumference of each track is a function of its radius, and because the same channel rate is used in such older drives, the in such older drives, the linear bit density changes as a fiction of track radius. In a contemporary embedded servo disk drive employing zone banding for data, the channel frequency for data changes from one band to another, with the highest channel frequency being used for the outermost zone band.
A patent application filed Mar. 10, 1997, in the United States Patent and Trademark Office, titled "DISK DRIVE EMPLOYING READ ERROR TOLERANT SYNC MARK DETECTION," in the name of Robert Cloke, and assigned to the assignee of this invention Docket No. K35A0195/Ser. No. 08/815,352!, discloses certain technology applicable to a zone-banded servo. The above-identified application includes a drawing FIG. 2B! showing a preferred format of data wedges and servo wedges for a zone-banded servo. The disclosure of the above-identified application is hereby incorporated by reference herein.
Although zone banded technology enables substantially higher storage density, it imposes challenges in requiring that certain circuitry in the channel be capable of rapidly changing its clock frequency as the head moves radially from zone band to zone band. These challenges are particularly difficult as to efforts to provide zone-banded servo.
As for the challenges involved for a frequency synthesizer, there will now be described the construction and operation of a representative prior art synthesizer.
With reference to FIG. 1, a typical prior art frequency synthesizer 1 receives a reference frequency signal (REF CLK) 3 as an input and produces a periodic output signal TCLK 5 as an output. Synthesizer 1 includes a feedforward state machine 7 (hereinafter referred to as "N divider 7"), a register 9 for storing a start value for N divider 7, and a closed-loop arrangement including a phase comparator 11, a charge pump 13, a filter 15, a voltage controlled oscillator (VCO) 17, and a feedback state machine 19 hereinafter referred to as "M divider 19." Synthesizer 1 also includes a register 21 for storing a start value for M divider 19.
Registers 9 and 21 are connected to a bus so that each can receive a selected programmed value from an external source such as a programmed microprocessor. These programmed values are repeatedly loaded into N divider 7 and M divider 19 to determine the ratio between the frequency of TCLK 5 and REF CLK 3.
N divider 7 produces an N.sub.0 signal and provides it to phase comparator 11. M divider 19 produces an M.sub.0 signal and provides it to phase comparator 11. Each of the N.sub.0 and M.sub.0 signals is a time-varying, binary-valued signal.
As for the structure that performs the functions indicated by the various blocks in FIG. 1, suitable structure is taught in various patents. For example, U.S. Pat. No. 4,494,021 shows a phase comparator in detail in its FIG. 7, and shows a charge pump, filter, and VCO in its FIG. 2.
With reference to FIG. 2, the flow of operation of synthesizer 1 will now be described in terms of a concrete example. The flow of operation involves parallel, independent frequency-division cycles. One such frequency-division cycle (for REF CLK 3 to N.sub.0) starts at block 200 with a start value being loaded into a register within N divider 7. The other such frequency-division cycle (for TCLK 5 to M.sub.0) starts at block 202 with a start value being loaded into a register within M divider 19. Assume that the register in N divider 7 is an 8-stage register that can be decremented in response to each pulse in REF CLK 3 from any preset value at or below the binary equivalent of the decimal number 255. Assume also that the register in M divider 19 is an 10-stage register that can be decremented in response to each pulse in TCLK 5 from any preset value at or below the binary equivalent of the decimal number 1023. Assume that the start value 40 is repeatedly loaded into the register in N divider 7, and the start value 128 is repeatedly loaded into the register within M divider 19. Assume also that the frequency of REF CLK 3 is 40 megahertz. Under these assumptions, N divider 7 will start a frequency-division cycle at the start value 40, be decremented 40 times, and then define a pulse in its N.sub.0 output. This repeating sequence is depicted in FIG. 2 in the loop defined by block 204 ("Decrement N") and the branches from test block 206 ("N=0?"). On the next pulse in REF CLK 3, the start value 40 will be loaded into the register again to start another frequency-division cycle at block 200. In parallel with the foregoing, M divider 19 will start a frequency-division cycle at the start value 128, be decremented 128 times, and then define a pulse in its M.sub.0 output. This repeating sequence is depicted in FIG. 2 in the loop defined by block 208 ("Decrement M") and the branches from test block 210 ("M=0?"). On the next pulse in TCLK 5, the start value 128 will be loaded into the register again to start another frequency-division cycle at block 202. Thus, the frequency of the N.sub.0 signal will be 1 megahertz (i.e., 40/40 megahertz) and the frequency of TCLK 5 will stabilize at 1 megahertz (i.e., 128/128 megahertz).
In FIG. 2, the operation of phase comparator 11 is depicted in blocks 212, 214, 216, 218, 220, and 222. For most of the parallel frequency-division cycles, neither the U (for pump Up) nor the D (for pump Down) output signals is asserted.
If the frequency-division cycle ending with N=0 occurs before the frequency-division cycle ending with M=0, phase comparator 11 will assert its U output. This is represented in FIG. 2 by blocks 212 ("Pump Down On?") and 216 ("Start Pump Up"). In other words, if the frequency-division cycle ending with M=0 has not completed immediately before block 212, the D output signal will not have been asserted and will remain negated, so the flow will follow the "No" path to block 216 in which the U signal will be asserted. If, on the other hand, the frequency-division cycle ending with M=0 completes immediately before block 212, the D output signal will have been and remain asserted, so the flow will follow the "YES" path to block 214 in which the D signal will be negated.
If the frequency-division cycle ending with M=0 completes before the frequency-division cycle ending with N=0, phase comparator 11 will assert its D output. This is represented in FIG. 2 by blocks 218 ("Pump Up On?") and 222 ("Start Pump Down"). In other words, if the frequency-division cycle ending with N=0 has not completed immediately before block 218, the U output signal will not have been asserted and will remain negated, so the flow will follow the "No" path to block 222 in which the D signal will be asserted. If, on the other hand, the frequency-division cycle ending with N=0 completes immediately before block 218, the U output signal will have been and remain asserted, so the flow will follow the "YES" path to block 220 in which the U signal will be negated.
A problem associated with a prior art frequency synthesizer involves the undesirable amount of time consumed in seeking from one selected frequency to a newly selected frequency and settling at the newly selected frequency. In an embedded-servo disk drive employing zone-banded recording, the frequency synthesizer in the channel chip needs to provide a selected one of a set of frequencies corresponding to a respective one of the zone bands. Whenever a track seek operation crosses a zone-band boundary, the frequency synthesizer receives a set of new start values from a microprocessor and needs to seek and settle its output frequency accordingly. To accomplish zone-banded servo, such frequency seeking and settling will need to be very rapid. As a general rule, any adjustment to the design of a prior art frequency synthesizer directed to reducing the amount of time it requires for frequency seeking and settling tends to make the frequency synthesizer unstable.
An aspect of the above-described problem involves an accumulation of phase error during the parallel, independent frequency-division cycles. With reference to waveforms A and B of FIG. 3, the N.sub.0 and M.sub.0 inputs to phase comparator 11 are shown for an example of operation immediately after new start values have been transferred into registers 9 and 21. An accumulating phase error, as indicated by 300a, 300b, 300c, 300d, and 300e in waveform B results during the immediately ensuing operation of prior art frequency synthesizer 1. The phase error between the N.sub.0 and M.sub.0 signals grows with each frequency-division cycle for an undesirably large number of frequency-division cycles. This accumulation of phase error inhibits rapid seeking to and settling at a new frequency for TCLK 5. This accumulation has the effect of adding another pole to the transfer function of the closed loop, whereby the loop is at least second order.
Another aspect of this problem relates to the extent of the accumulation of phase error being such that one of the dividers can start and end two frequency-division cycles before the end of a frequency-division cycle for the other divider.
To illustrate the foregoing point with an example, assume that synthesizer 1 has been operating such that N-divider 7 frequency-divides a 40 MHz REF CLK 3 by 40, and that M-divider 19 frequency-divides a 100 MHz TCLK 5 by 100. Assume at an instance in time referred to herein as time 0, a new start value is transferred to register 21 such that thereafter M-divider 19 will frequency-divide TCLK 5 by 128. Assume for simplicity also that the transfer function from the time error in nanoseconds between the end of the N.sub.0 cycle and the end of the M.sub.0 cycle) to the change in VCO frequency is a constant (0.0037 Hz per nanoseconds).
Table 1 set forth below lists the following data for this example. One column lists the cycle number for N-divider 7. Another column lists the cycle number for M-divider 19. Another column lists elapsed time from time 0 for specific events, viz., the times at which N-divider 7 ends its frequency-division cycle and the times at which M-divider 19 ends its frequency-division cycle. Another column lists the frequency of VCO 17. Another column lists the error magnitude (the difference in time between the ends of the frequency-division cycles of N-divider 7 and M-divider 19. Another column lists the percentage error between the current and target frequencies of VCO 17.
TABLE 1 ______________________________________ ELAPSED VCO N M TIME FREQ ERROR % ______________________________________ 1 END OF N 1000 100.00 22% 1 END OF M 1280 280 2 END OF N 2000 101.04 21% 2 END OF M 2547 547 3 END OF N 3000 103.06 19% 3 END OF M 3789 789 4 END OF N 4000 105.98 17% 4 END OF M 4997 997 5 END OF N 5000 109.67 14% 6 END OF N 6000 109.67 14% 5 END OF M 6164 1164 7 END OF N 7000 113.97 11% 6 END OF M 7287 287 8 END OF N 8000 115.03 10% 7 END OF M 8400 400 9 END OF N 9000 116.51 9% 8 END OF M 9498 498 10 END OF N 10000 118.36 8% 9 END OF M 10580 580 11 END OF N 11000 120.50 6% 10 END OF M 11642 642 12 END OF N 12000 122.88 4% 11 END OF M 12684 684 13 END OF N 13000 125.41 2% 12 END OF M 13704 704 14 END OF N 14000 128.01 0% 13 END OF M 14704 704 15 END OF N 15000 130.62 -2% 14 END OF M 15684 684 16 END OF N 16000 133.15 -4% 15 END OF M 16646 646 17 END OF N 17000 135.54 -6% 16 END OF M 17590 590 ______________________________________
As the first row of Table 1 indicates, at the end of the first frequency-division cycle of N-divider 7, VCO 17 continues operating at 100 MHz which constitutes an initial percentage error of 22%, measured against the target frequency of 128 MHz. Whereas the first frequency-division cycle of N-divider 7 ends after a total elapsed time of 1000 nanoseconds, the first frequency-division cycle of M-divider 19 ends after a total elapsed time of 1280 nanoseconds. The first measured error magnitude is 280 nanoseconds. Based on the assumed transfer function VCO 17 then operates at a higher frequency of 101.04 MHz. The error magnitude accumulates cycle to cycle from 280 nanoseconds to 997 nanoseconds by the end to the fourth frequency-division cycle for M-divider 19. At this stage of operation, the error magnitude has accumulated to such an extent that N-divider 7 ends both its fifth and sixth frequency division cycles before the end of the fifth frequency-division cycle of M-divider 21. Throughout this time, the percentage error remains at 14%. As indicated by the rows at the bottom of Table 1, synthesizer 1 can "overshoot" the target frequency and then begin to "hunt" a steady state value.
In view of the foregoing, it is desirable to provide a frequency synthesizer that more rapidly completes a seek and settle operation in shifting its output frequency from one selected value to another.